1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a logic circuit for logically processing a delay signal and a data delay circuit used in a data readout circuit of a semiconductor memory.
2. Description of the Related Art
A conventional semiconductor memory, for example, an EPROM (electrically programmable nonvolatile semiconductor memory) is generally constructed as shown in FIG. 1. In FIG. 1, Ai (i=0 to k) is a row address input signal and is input to a row decoder circuit 2 after being amplified and shaped by a row address buffer circuit 1. Bj (j=k+1 to n) is a column address input signal and is input to a column decoder circuit 4 after being amplified and shaped by a column address buffer circuit 3. The row decoder circuit 2 selects one of the word lines of a memory cell array 5 in which memory cells for storing data are arranged and the column decoder circuit 4 controls a column selection gate 6 to select one of the bit lines of the memory cell array 5. Thus, one of the memory cell transistors is selected from the memory cell array 5 and data of the selected memory cell is amplified and sensed by a sense amplifier circuit 7. Data sensed by the sense amplifier circuit 7 is read out to the exterior of the chip via a output buffer 8.
The inventors of this invention proposed a highly reliable semiconductor integrated circuit in Japanese Patent Application No. 63-291969 in which a data delay circuit 9 and a data latch circuit 10 are connected between the sense amplifier circuit 7 and the output buffer circuit 8 as shown in FIG. 1, and fluctuation in the power source voltage at the time of change of output data or an erroneous operation of the internal circuit of the integrated circuit due to noise input from the exterior can be prevented by controlling the data delay circuit 9, data latch circuit 10 and output buffer control circuit 11 according to an address change detecting signal ATD and the driving ability of an output stage transistor can be enhanced, thereby making it possible to increase the operation margin of the integrated circuit chip with respect to the power source voltage fluctuation and noise without lowering the data readout speed.
In the above semiconductor integrated circuit, outputs of the row address buffer circuit 1 and the column address buffer circuit 3 are input to corresponding address change detection circuits 12 and pulse outputs of the address change detection circuits 12 are supplied to a OR circuit 16 so that a pulse signal (address change detection signal) ATD having a preset pulse width may be generated when at least one of the address input signals Ai and Bj is changed and the signal ATD is input to a control circuit 13.
The control circuit 13 generates a signal ATDdly for controlling the output buffer control circuit 11, signals DLP and DLP for controlling the data latch circuit 10 and signals A and B for controlling the data delay circuit 9.
The data delay circuit 9 includes a delay circuit 91 supplied with an output signal d* of the sense amplifier circuit 7 and a bypass circuit 92 for bypassing the signal d*. In the delay circuit 9, since the input signal d* is output with preset delay time (for example, several tens of nanoseconds) when the delay circuit 91 is operated, noise can be absorbed by the data delay circuit 9 even when the noise superposed on the output signal d* by the erroneous operation of the sense amplifier circuit 7 caused by noise input from the exterior or fluctuation in the power source voltage at the time of output data change and if the duration of the noise is less than the preset delay time. That is, the data delay circuit 9 functions as a noise canceller (this state is hereinafter referred to as an operative state of the data delay circuit 9). Further, when the address change detection signal ATD is changed and the data delay circuit controlling signals A and B are changed, the output signal d* of the sense amplifier circuit 7 is instantaneously output via the bypass circuit 92 without any delay (this state is hereinafter referred to as a non-operative state of the data delay circuit 9).
Output data d*dly of the data delay circuit 9 is input to the data latch circuit 10. When the address change detection signal ATD is changed in response to the address change and data latch controlling signals DLP and DLP are changed, the data latch circuit 10 latches data corresponding to the address before the address change has occurred for a preset period of time and outputs the latched data d*lat via the output buffer circuit 8. The state in which data is latched by the data latch circuit 10 is hereinafter referred to as an operative state of the data latch circuit 10 and the state in which no data is latched in the data latch circuit 10 is hereinafter referred to as a non-operative state of the data latch circuit 10.
A CE buffer circuit 14 shapes and amplifies a chip enable input signal (or chip selection signal) CE from the exterior of the integrated circuit and creates an internal chip enable signal CE* for setting the integrated circuit chip into an operative state or stand-by state.
A CE equalization controlling circuit 15 generates a control signal (complementary signals ST and ST) for controlling the sense amplifier circuit 7 in order to enhance the data readout speed when the chip enable input signal CE is changed and data is read out. That is, in a case where the chip enable input signal CE is changed and data is read out, the readout operation is delayed by a period of time required for the integrated circuit chip to be set into the operative state by the internal chip enable signal CE* in comparison with a case wherein the address input signal is changed and then data is read out. In order to solve the above problem, the potential of a column line to which data read out from the memory cell is supplied is set to an intermediate potential between the potentials corresponding to "1" and "0" of the data of the memory cell by use of the signals ST and ST in a period of time after the signal CE is changed and the signal CE* is set to the active state until a memory cell corresponding to the input address is selected. In this case, since the potential of the column line is changed from the intermediate potential level to the "1" potential level or "0" potential level, data can be more rapidly read out.
Further, the output buffer control circuit 11 shapes and amplifies an output enable input signal OE from the exterior of the integrated circuit and generates an internal output buffer control signal (complementary signals OE* and OE*) for setting the output buffer circuit 8 into the data readout permissible state (operative state) or the non-operative state.
Next, the operation of the memory shown in FIG. 1 is explained with reference to the timing signal waveforms shown in FIG. 2. When the address input signals Ai and Bj are changed to read out data from the memory cell, a memory cell corresponding to the address input is selected and data thereof is read out by the sense amplifier 7. In this case, the change of the address input signal is detected by the address change detection circuit 12 and the pulse signal ATD is kept at the "1" level for a preset period of time. When the signal ATD is input to the control circuit 13, the signal ATDdly, data latch circuit control signals (DLP, DLP) and data delay circuit control signals (A, B) are changed in response to the signal ATDdly. For example, when the address input signal is changed and the pulse signal ATD is set to the "1" level, the signal ATDdly is set to the "1" level and the signal DLP is set to the "1" level in response to change of the signal ATDdly. As a result, the data latch circuit 10 is set into the operative state and data d*dy (output of the data delay circuit 9) of the memory cell at the address set before the address input signal is changed is latched for a preset period of time. The latched data d*lat is output via the output buffer circuit 8. When the address signal is changed, the signal B is set to the "0" level and the data delay circuit 9 is set into the non-operative state, thereby permitting output data d* from the sense amplifier 7 to be instantaneously output via the bypass circuit 92. When the signal ATD is set to the "0" level, the signal ATDdly is changed to the "0" level after a preset period of time has elapsed. For example, the preset period of time is set to a length of time from the change of the address input signal until data of a memory cell corresponding to the address is determined by the sense amplifier circuit 7 and bypass circuit 92. The signal DLP is set to the "0" level by the change of the signal ATDdly to the "0" level and the data latch circuit 10 is set into the non-operative state. When the data latch circuit 10 is set into the non-operative state, the output data d*dly of the data delay circuit 9 is output via the data latch circuit 10 and output buffer circuit 8. When the signal DLP is set to the "0" level, the signal B is set to the "1" level and the data delay circuit 9 is set into the operative state.
When the address input signal is thus changed and data from the output buffer circuit 8 is output, the data delay circuit 9 connected to the output section of the sense amplifier circuit 7 is set into the operative state and the data delay circuit 9 functions as a noise canceller, thus providing an integrated circuit having a large operation margin.
Generally, in the semiconductor memory, it is necessary to drive a large capacitor externally provided, for example, a load capacitor of approx. 100 pF. For this reason, the current driving ability of an output stage transistor of the output buffer circuit 8 for outputting internal data of the semiconductor memory to the exterior is set to be extremely large so as to satisfactorily drive the large load capacitor.
Next, an example of the output buffer circuit 8 is shown in FIG. 3 and the operation thereof and problems associated therewith are explained. The output data d*lat from the data latch circuit 10 (FIG. 1) is supplied to an input terminal 51 of the output buffer circuit 8. In a period in which the output buffer circuit is operated, a control signal OE* is set to the "0" level and a control signal OE* is set to the "1" level. Therefore, a P-channel MOS transistor 52 controlled by the control signal OE* is turned on and an N-channel MOS transistor 53 is turned off. As a result, the input data d*lat is supplied to the gate of an output stage P-channel MOS transistor 58 via a CMOS inverter constructed by a P-channel MOS transistor 54 and an N-channel MOS transistor 55 and a CMOS inverter constructed by a P-channel MOS transistor 56 and an N-channel MOS transistor 57.
An N-channel MOS transistor 59 controlled by the control signal OE* is turned on and a P-channel MOS transistor 60 is turned off. As a result, the input data d*lat is supplied to the gate of an output stage N-channel MOS transistor 65 via a CMOS inverter constructed by a P-channel MOS transistor 61 and an N-channel MOS transistor 62 and a CMOS inverter constructed by a P-channel MOS transistor 63 and an N-channel MOS transistor 64. In this case, the sources of the output stage transistors 58 and 65 are respectively connected to a positive power source voltage terminal Vcc and a ground potential terminal Vss and the drains thereof are connected to an output terminal 66.
In the above output buffer circuit, one of the output stage transistors 58 and 65 is turned on according to the level of the input data d*lat. When the P-channel MOS transistor 58 is kept in the ON state, a load capacitor 67 connected to the output terminal 66 is charged to a Vcc potential, and when the N-channel MOS transistor 65 is kept in the ON state, it is discharged to a Vss potential. At this time, in order to enhance the rising speed and falling speed of data Dout to be output from the output terminal 66 by charging or discharging the load capacitor with a large current, the element sizes of the output stage transistors 58 and 65 are set large and the conductance thereof is set to a large value.
In a case where the semiconductor integrated circuit having the above output buffer circuit is incorporated into a system product, the power source voltage Vcc and ground potential Vss are supplied to the semiconductor integrated circuit via wirings from a power source unit 70. Therefore, when a large current flows in the Vcc and Vss wirings, the Vcc potential or Vss potential will largely vary by an influence of inductances 71 and 72 of the Vcc and Vss wirings. That is, if the inductance component existing in the wirings is L and the rate of variation in the current flowing in the wiring with respect to time is expressed by di/dt, then the potential variation .DELTA.v expressed by the following equation occurs in the wiring. EQU .DELTA.v=L(di/dt) . . . (1)
FIG. 4 shows voltage and current waveforms of portions in the above output buffer circuit. In this case, Va indicates a gate potential of the output stage P-channel MOS transistor 58, Vb indicates a gate potential of the output stage N-channel MOS transistor 65, Is indicates a drain current of the P-channel MOS transistor 58, It indicates a drain current of the N-channel MOS transistor 65, and Dout indicates an output signal.
As shown in FIG. 4, when the level of the input data d*lat has varied, the gate potential Va of the output stage P-channel MOS transistor 58 and the gate potential Vb of the N-channel MOS transistor 65 are changed and the transistors 58 and 65 effect the switching operations. As s result, the drain current Is of the transistor 58 or the drain current It of the transistor 65 flows to cause potential variation in the Vcc potential or the Vss potential.
When data is thus output from the output buffer circuit, a large current flows in the output stage so as to cause potential variation in the power source voltage Vcc or ground potential Vss (which is hereinafter referred to as power source variation) in the internal portion of the integrated circuit, and an erroneous operation is caused in the integrated circuit by the power source variation. Since it is necessary to conduct a larger current when the integrated circuit is required to have a high operation speed and it is necessary to charge or discharge an external load capacitor in a short period of time, an erroneous operation caused by the charging or discharging current with respect to the load capacitor tends to more easily occur.
Next, an example of the data delay circuit 9 is shown in FIG. 5 and the function thereof as a noise canceller is explained. In the data delay circuit 9 shown in FIG. 5, output data d* from the sense amplifier 7 is input to the delay circuit 91 and the bypass circuit 92 via an inverter I9. In the delay circuit 91, an output of the inverter I9 is input to an inverter I10. The output terminal of the inverter I10 is connected to an inverter I11 via a transfer gate TG2 constructed by a parallel circuit of an N-channel transistor whose gate is applied with the Vcc potential and a P-channel transistor whose gate is applied with the Vss potential. A capacitor CP2 constructed by a P-channel transistor whose source and drain are applied with the Vcc potential and a capacitor CN2 constructed by an N-channel transistor whose source and drain are applied with the Vss potential are connected to a line connected between the transfer gate TG2 and the inverter I11.
The circuit 92 is connected in parallel with the delay circuit 91 and an output of the inverter I9 is input to an inverter I10'. The output terminal of the inverter I10' is connected to one end of a transfer gate TG3 constructed by a parallel circuit of a P-channel transistor whose gate is supplied with the signal B and an N-channel transistor whose gate is supplied with the signal A. The other end of the transfer gate TG3 is connected to an input terminal (node N1) of a clocked inverter CI1. The clocked inverter CI1 includes P- and N-channel transistors constituting an inverter section, a P-channel transistor series-connected with the inverter section and turned on by the signal B of "0" level and an N-channel transistor series-connected with the inverter section and turned on by the signal A of "1" level. Further, the other end of the transfer gate TG3 is also connected to the input terminal (node N1) of the inverter I11 of the delay circuit 91. The output terminal of the clocked inverter CI1 and the output terminal of the inverter I11 are connected together and the common connection node is connected to an inverter I12.
The delay circuit 91 receives an output from the inverter I9 and outputs the same with a preset period of delay time (for example, several tens of nanoseconds). The output is supplied as an output of the data delay circuit 9 via the inverters I11 and I12. Therefore, even when noise is superposed on the output of the inverter I9, the noise can be absorbed by the delay circuit 91 if the duration of noise is less than the above preset period of time. That is, the delay circuit 91 functions as a noise canceller.
Since the inverter I10' and transfer gate TG3 of the circuit 92 are designed to have extremely larger driving abilities in comparison with the inverter I10 and transfer gate TG2 of the delay circuit 9, the transfer gate TG3 is turned on and the clocked inverter CI1 is activated so as to permit an input from the inverter I9 to be instantaneously output when the address signal is changed and the signals A and B are respectively set to the "1" and "0" levels. The output is supplied as an output of the data delay circuit 9 via the inverter I12. Therefore, the circuit 92 functions as a bypass circuit for the delay circuit 91.
Next, a problem occurring when an erroneous operation of the sense amplifier circuit 7 is caused by the power source variation is explained with reference to FIGS. 6A and 6B.
In general, in order to cause the sense amplifier circuit 7 to read out data at a high speed, a potential difference between the two input nodes thereof is set to a small value. For this reason, the response speeds (following speeds) for variations in the Vcc potential and Vss potential become different from each other by a difference between the parasitic capacitances of the two input nodes. The relation between the potentials of the two input nodes is reversed several times by the difference between the response speeds and erroneous data is output from the sense amplifier circuit. That is, an erroneous operation occurs in the data detection by the sense amplifier circuit 7. The erroneous operation is illustrated by portions of data d* surrounded by broken lines in FIGS. 6A and 6B. When pulse noises are superposed on input data d* of the data delay circuit 9 shown in FIG. 5, the node N1 which is to be charged to "1" or discharged to "0" as shown in FIG. 6A or 6B starts to be charged or discharged to a preset stable potential. When the number of pulse noises is small, the amount of charges to be charged or discharged is small, but when the number of pulse noises is large, the potential of the node N1 will be charged or discharged to the preset stable potential. When a potential used as a reference for determining whether the potential level of an input signal is "0" or "1" level is set higher than the above stable potential in the data delay circuit shown in FIG. 5 and if input data d* of the data delay circuit is set at the "0" level, a large number of noise pulses are input as shown in FIG. 6B and the inverter I11 determines that the potential of the node N1 is at the "0" level even if the node N1 is charged to a preset potential level. That is, no erroneous operation occurs. In contrast, however, when input data d* is set at the "1" level as shown in FIG. 6A and if the above pulse noises are input, the node N1 is gradually discharged and the potential thereof reaches the above stable potential level. However, at this time, since the inverter I11 is designed to determine the stable potential as the "0" level, the inverter I11 will determine the logic level of the node N1 as the "0" level. That is, an erroneous operation occurs so as to permit erroneous data to be output from the data delay circuit. Further, erroneous data will be output from the output buffer circuit 8.
The above erroneous operation tends to more easily occur when the potential difference between the two input nodes of the sense amplifier circuit 7 is smaller. However, in order to enhance the readout speed, it is preferable to set the potential difference between the two nodes as small as possible, and therefore, the above erroneous operation will be more easily occur in a semiconductor memory which is required to have a higher operation speed.
As described above, the conventional semiconductor integrated circuit has a problem that a data delay circuit is erroneously operated when an erroneous operation occurs in the data detection by the sense amplifier circuit at the time of power source variation, and as a result, erroneous data is output from the output buffer circuit.